View GS9035ACPJ_8178571.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: november 2000 document no. 522 - 41- 04 data sheet gs9035a features ? adjustment-free operation auto-rate selection for 5 smpte data rates: 143, 177, 270, 360, 540mb/s data rate indication output serial data output mute when pll is not locked immune to harmonic locking operation independent of sav/eav sync signals low jitter, low power single external vco resistor for operation with five input data rates large input jitter tolerance: typically 0.45 ui beyond loop bandwidth power savings mode (output serial clock disable) system friendly: serial clock remains active when data outputs muted robust lock detect applications the gs9035a is used for clock and data recovery, and jitter elimination for all high speed serial digital interface applications involving smpte 259m and other data standards. description the gs9035a is a high performance clock and data recovery ic designed for serial digital data. the gs9035a receives either single-ended or differential pecl data and outputs differential pecl clock and retimed data signals. the gs9035a can operate in either auto or manual rate selection mode. in auto mode the gs9035a is ideal for multi-rate serial data protocols such as smpte 259m. in this mode the gs9035a automatically detects and locks onto the incoming data signal. for single rate data systems, the gs9035a can be configured to operate in manual mode. in both modes, the gs9035a requires only one external resistor to set the vco centre frequency and provides adjustment free operation. the gs9035a has dedicated pins to indicate lock and data rate. in addition, an internal muting function forces the serial data outputs to a static state when input data is not present or when the pll is not locked. the serial clock outputs can also be disabled resulting in a 10% power savings. the gs9035a is packaged in a 28 pin plcc and operates from a single +5 or -5 volt power supply. block diagram ordering information part number package temperature GS9035ACPJ 28 pin plcc 0c to 70c gs9035actj 28 pin plcc tape 0c to 70c ddi/ddi lf+ lfs lf- cbg r vco carrier detect phaselock harmonic frequency acquisition vco division 3 bit counter lock sdo sdo clk_en sco sco smpte auto/man sso ss1 ss2 cosc 2 phase detector charge pump decoder logic genlinx ? ii gs9035a serial digital reclocker
gennum corporation 522 - 41- 04 2 gs9035a fig. 1 jitter measurement test setup absolute maximum ratings parameter value supply voltage (v s ) 5.5v input voltage range (any input) v cc + 0.5 to v ee - 0.5v operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature (soldering, 10 sec) 260c dc electrical characteristics v cc = 5.0v, v ee = 0v, t a = 25 unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf. parameter condition min typical 1 max units notes test level supply voltage 4.75 5.00 5.25 v 1 supply current clk_en = 0 - 90 110 ma 1 clk_en = 1 - 105 120 ma ddi/ddi common mode input voltage range v ee + (v diff /2) 0.4 to 4.6 v cc - (v diff /2) v 2 1 ddi/ddi differential input drive 200 800 2000 mv 1 auto/man , smpte, ss[2:0] input voltage high 2.0 - - v 1 low - - 0.8 clk_en input voltage high 2.5 - - v 1 low - - 0.8 lock output sink current 500 - - a 3 1 ss[2:0] output voltage high 4.4 4.7 - v 1 low - 0.2 0.4 ss[2:0] source current auto mode 180 300 - a 1 ss[2:0] sink current auto mode 0.6 1 - ma ss[2:0] source current manual mode - 0 - a 4 1 ss[2:0] sink current manual mode - 0.8 5 a clk_en source current low - 26 55 a 1 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. notes 1. typical - measured on eb-rd35a board, t a = 25c. 2. v diff is the differential input signal swing. 3. lock is an open collector output and requires an external pullup resistor. 4. pins ss[2:0] are outputs in auto mode and inputs in manual mode. pattern 2 23 -1 clk data di di sdo ch-1 trig tektronix gigabert 1400 gennum test board tektronix csa803
gennum corporation 522 - 41- 04 3 gs9035a ac electrical characteristics v cc = 5.0v, v ee = 0v, t a = 25c unless otherwise stated, r lf = 1.8k, c lf1 = 15nf, c lf2 = 3.3pf parameter condition min typical 1 max units notes test level serial data rate sdi 143 - 540 mb/s 1 intrinsic jitter psuedorandom (2 23 - 1) 270mb/s - 185 see figure 6 ps p-p 2 4 540mb/s - 164 intrinsic jitter pathological (sdi checkfield) 270mb/s - 462 see figure 7 ps p-p 2 1 360mb/s - 308 540mb/s - 260 input jitter tolerance 270mb/s 0.40 0.56 - ui p-p 3 1 540mb/s 0.35 0.43 - lock time synchronous switch t switch < 0.5s, 270mb/s - 1 - s 4 7 0.5s < t switch < 10ms - 1 - ms t switch > 10ms - 4 - ms lock time asynchronous switch loop bandwidth = 6mhz at 540 mb/s - 10 - ms 5 7 carrier loss time r lock = 10k, c load =5pf 0.5 1 2 s 6 7 sdo to sco synchronization -200 0 200 ps 7 sdo, sco output signal swing 75 ? dc load 600 800 1000 mv p-p 1 sdo, sco rise and fall times 20% - 80% 200 300 400 ps 7 notes 1. typical - measured on eb-rd35a board, t a = 25c. 2. characterized 6 sigma rms. 3. ijt measured with sinusoidal modulation beyond loop bandwidth (at 6.5mhz). 4. synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie : line 10 switching for component ntsc). 5. asynchronous switching refers to switching the input data from one source to another source which is at a different data rate . 6. carrier loss time refers to the response of the sdo output from valid re-clocked input data to mute mode when the input signa l is removed. test level 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correl ated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product.
gennum corporation 522 - 41- 04 4 gs9035a pin connections pin descriptions number symbol type description 1,7,8,11,27 v ee i most negative power supply connection. 2 cosc i timing control capacitor for internal system clock. 3 lock o lock indication. when high, the gs9035a is locked. lock is an open collector output and requires an external 10k pullup resistor. 4 smpte i smpte/other rate select. 5, 6 ddi/ddi i digital data input (differential ecl/pecl). 9v cc1 i most positive power supply connection. 10 auto/man i auto or manual mode select. ttl/cmos compatible input. 12 lf+ i loop filter component connection. 13 lfs i loop filter component connection. 14 lf- i loop filter component connection. 15 r vco _rtn i r vco return. 16 r vco i frequency setting resistor. 17 cbg i internal bandgap voltage filter capacitor. 18 v cc2 i most positive power supply connection. 19 - 21 ss[2:0] i/o data rate indication (auto mode) or data rate select (manual mode). ttl/cmos compatible i/o. in auto mode these pins can be left unconnected. 22, 23 sco /sco o serial clock output. sco /sco are differential current mode outputs and require external 75 ? pullup resistors. 24, 25 sdo /sdo o serial data output. sdo /sdo are differential current mode outputs and require external 75 ? pullup resistors. 26 v cc3 i most positive power supply connection. 28 clk_en i clock enable. when high, the serial clock outputs are enabled. ddi ddi v ee v ee v cc1 auto/man v ee sdo sdo sco sco sso ss1 ss2 smpte lock cosc v ee clk_en v ee v cc3 gs9035a top view lf+ lfs lf- r vco _rtn r vco cbg v cc2 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26
gennum corporation 522 - 41- 04 5 gs9035a typical performance curves (v s = 5v, t a = 25c unless otherwise shown.) fig. 2 intrinsic jitter (2 23 -1 pattern) 30mb/s fig. 3 intrinsic jitter (2 23 -1 pattern) 143mb/s fig. 4 intrinsic jitter (2 23 -1 pattern) 270mb/s fig. 5 intrinsic jitter (2 23 -1 pattern) 540mb/s fig. 6 intrinsic jitter - pseudorandom (2 23 -1) fig. 7 intrinsic jitter - pathological sdi checkfield 0 200 400 600 800 1000 1200 1400 1600 1800 2000 100 200 300 400 500 600 sdi data rate (mb/s) jitter (ps) qa output jitter limit, sample tested max typical min t a =0 to 70?c, v cc =4.75 to 5.25v for the typical range typical range, characterized 0 200 400 600 800 1000 1200 1400 1600 1800 2000 100 200 300 400 500 600 sdi data rate (mb/s) typical min jitter (ps p-p) max qa output jitter limit, sample tested t a = 0 to 70 ? c, v cc = 4.75 to 5.25v for the typical range typical range, characterized
gennum corporation 522 - 41- 04 6 gs9035a fig. 8 typical input jitter tolerance (characterized) fig. 9 typical ijt vs. temperature (vcc=5.0v) (characterized) detailed description the gs9035a receives either a single-ended or differential pecl serial data stream at the ddi and ddi inputs. it locks an internal clock to the incoming data and outputs the differential pecl retimed data signal and recovered clock on outputs sdo /sdo and sco /sco respectively. the timing between the input, output, and clock signals is shown below. fig. 10 input/output clock signal timing the gs9035a reclocker contains four main functional blocks: the phase locked loop, auto/manual data rate select, frequency acquisition, and logic circuit. 1. phase locked loop (pll) the phase locked loop locks the internal pll clock to the incoming data rate. a simplified block diagram of the pll is shown below. the main components are the vco, the phase detector, the charge pump, and the loop filter. fig. 11 simplified diagram of the pll 1.1. vco the vco is a differential low phase noise, factory trimmed design that provides increased immunity to pcb noise and precise control of the vco center frequency. the vco operates between 30 and 540mb/s and has a pull range of -13 +25% about the center frequency depending on the signal data rate. a single low impedance external resistor, r vco , sets the vco center frequency (see figure 12). the low impedance r vco minimizes thermal noise and reduces the pll's sensitivity to pcb noise. for a given r vco value, the vco can oscillate at one of two frequencies. when smpte = ss0 = logic 1, the vco center frequency corresponds to the l curve. for all other smpte/ss0 combinations, the vco center frequency corresponds to the h curve ( h is approximately 1.5 x l ). 0 0.1 0.2 0.3 0.4 0.5 0.6 100 200 300 400 500 600 data rate (mb/s) ijt (ui) t a = 0 to 70 ? c, v cc = 4.75 to 5.25v 0.200 0.250 0.300 0.350 0.400 0.450 0.500 0.550 0.600 0 10203040506070 temperature (c ? ) ijt (ui) 143mb/s 177mb/s 270mb/s 360mb/s 540mb/s ddi sdo sco 50% ddi/ddi lf+ lfs lf- r vco vco division r lf c lf1 c lf2 2 phase detector internal pll clock charge pump loop filter
gennum corporation 522 - 41- 04 7 gs9035a fig. 12 vco frequency vs. r vco the recommended r vco value for auto rate smpte 259m applications is 365 ? . the vco and an internal divider generate the pll clock. divider moduli of 1, 2, and 4 allow the pll to lock to data rates from 143mb/s to 540mb/s. the divider modulus is set by the auto/man , smpte, and ss[2:0] pin (see auto/manual data rate select section for further details). in addition, a manually selectable modulus 8 divider allows operation at data rates as low as 30mb/s. when the input data stream is removed for an excessive period of time (see ac electrical characteristics table), the vco frequency can drift from the previously locked frequency up to the maximum shown in table 1. 1.2. phase detector the phase detector compares the phase of the pll clock with the phase of the incoming data signal and generates error correcting timing pulses. the phase detector design provides a linear transfer function between the input phase and output timing pulses maximizing the input jitter tolerance of the pll. 1.3. charge pump the charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. a unique differential charge pump design ensures that the output phase does not drift when data transitions are sparse. this makes the gs9035a ideal for smpte 259m applications where pathological signals have data transition densities of 0.05. 1.4. loop filter the loop filter integrates the charge pump packets and produces a vco control voltage. the loop filter is comprised of three external components which are connected to pins lf+, lfs, and lf-. the loop filter design is fully differential giving the gs9035a increased immunity to pcb board noise. the loop filter components are critical in determining the loop bandwidth and damping of the pll. choosing these component values is discussed in detail in the pll design guidelines section. recommended values for smpte 259m applications are shown in the typical application circuit diagram. 2. frequency acquisition the core pll is able to lock if the incoming data rate and the pll clock frequency are within the pll capture range (which is slightly larger than the loop bandwidth). to assist the pll to lock to data rates outside of the capture range, the gs9035a uses a frequency acquisition circuit. the frequency acquisition circuit sweeps the vco control voltage such that the vco frequency changes from -10% to +10% of the center frequency. figure 13 shows a typical sweep waveform. fig. 13 typical sweep form the vco frequency starts at point a and sweeps up attempting to lock. if lock is not established during the up sweep, the vco is then swept down. the system is designed such that the probability of locking within one cycle period is greater than 0.999. if the system does not lock within one cycle period, it will attempt to lock in the subsequent cycle. in manual mode, the divider modulus is fixed for all cycles. in auto mode, each subsequent cycle is based on a different divider moduli as determined by the internal 3-bit counter. table 1: frequency drift range (when pll loses lock) loses lock from min (%) max(%) 143mb/s lock -21 21 177mb/s lock -12 26 270mb/s lock -13 28 360 mb/s lock -13 24 540 mb/s lock -13 28 0 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 1400 1600 1800 vco frequency (mhz) r vco (?) h l smpte=1 sso=1 v lf t swp t cycle t cycle = t swp + t sys t sys a
gennum corporation 522 - 41- 04 8 gs9035a the average sweep time, t swp , is determined by the loop filter component, c lf1 , and the charge pump current, cp : the nominal sweep time is approximately 121s when c lf1 = 15nf and cp = 165a (r vco = 365 ? ). an internal system clock determines t sys ( see section 7, logic circuit ). 3. logic circuit the gs9035a is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. that is, the system clock is completely independent of the incoming data rate. the system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the pll. the period of the system clock is set by the cosc capacitor and is t sys = 9.6 x 10 4 x cosc [seconds] the recommended value for t sys is 450s (cosc = 4.7nf). 4. auto/manual data rate select the gs9035a can operate in either auto or manual data rate select mode. the mode of operation is selected by a single input pin (auto/man ). 4.1. auto mode (auto/man = 1) in auto mode, the gs9035a uses a 3-bit counter to automatically cycle through five (smpte=1) or three (smpte=0) different divider moduli as it attempts to acquire lock. in this mode, the ss[2:0] pins are outputs and indicate the current value of the divider moduli according to table 2. note that for smpte = 0 and divider moduli of 2 and 4, the pll can correctly lock for two values of ss[2:0]. 4.2. manual mode (auto/man = 0) in manual mode, the gs9035a divider moduli is fixed. in this mode, the ss[2:0] pins are inputs and set the divider moduli according to table 3. table 2: data rate indication in auto mode auto/man = 1 (auto mode) ? h , ? l = vco center frequency as per figure 12 smpte ss[2:0] divider moduli pll clock 1 000 4 h /4 1 001 2 l /2 1 010 2 h /2 1 011 1 l 1 100 1 h 1 101 - - 1 110 - - 1 111 - - t swp 4 3 -- - c lf1 i cp ------------ - onds sec [] = 0 000 4 h /4 0 001 4 h /4 0 010 2 h /2 0 011 2 h /2 0 100 1 h 0 101 - - 0 110 - - 0 111 - - table 3: data rate select in manual mode auto/man = 0 (manual mode) ? h , ? l = vco center frequency as per figure 8 smpte ss[2:0] divider moduli pll clock 1 000 4 h /4 1 001 2 l /2 1 010 2 h /2 1 011 1 l 1 100 1 h 1 101 8 l /8 1 110 8 h /8 1 111 - - 0 000 4 h /4 0 001 4 h /4 0 010 2 h /2 0 011 2 h /2 0 100 1 h 0 101 1 h 0 110 8 h /8 0 111 - - table 2: data rate indication in auto mode (continued) auto/man = 1 (auto mode) ? h , ? l = vco center frequency as per figure 12 smpte ss[2:0] divider moduli pll clock
gennum corporation 522 - 41- 04 9 gs9035a 5. locking the gs9035a indicates lock when three conditions are satisfied: 1. input data is detected. 2. the incoming data signal and the pll clock are phase locked. 3. the system is not locked to a harmonic. the gs9035a defines the presence of input data when at least one data transition occurs every 1s. the gs9035a assumes that it is not locked to a harmonic if the pattern 101 or 010 (in the reclocked data stream) occurs at least once every t sys /3 seconds. using the recommended component values, this corresponds to approximately 150s. (in an harmonically locked system, all bit cells are double clocked and the above patterns become 110011 and 001100 , respectively.) 6. lock time the lock time of the gs9035a depends on whether the input data is switching synchronously or asynchronously. synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). asynchronous switching refers to the case where the input data to the gs9035a is changed from one source to another source which is at a different data rate. when input data to the gs9035a is removed, the gs9035a latches the current state of the counter (divider modulus). therefore, when data is reapplied, the gs9035a begins the lock procedure at the previous locked data rate. as a result, in synchronous switching applications, the gs9035a locks very quickly. the nominal lock time depends on the switching time and is summarized in the table below: in asynchronous switching applications (including power up) the lock time is determined by the frequency acquisition circuit as described in section 2, frequency acquisition . in manual mode, the frequency acquisition circuit may have to sweep over an entire cycle (depending on initial conditions) to acquire lock resulting in a maximum lock time of 2t cycle + 2t sys . in auto tune mode, the maximum lock time is 6t cycle + 2t sys since the frequency acquisition circuit may have to cycle through 5 possible counter states (depending on initial conditions) to acquire lock. the nominal value of t cycle for the gs9035a operating in a typical smpte 259m application is approximately 1.3ms. the gs9035a has a dedicated lock output (pin 3) indicating when the device is locked. it should be noted that in synchronous switching applications where the switching time is less than 0.5s, the lock output will not be de-asserted and the data outputs will not be muted. 7. output data muting the gs9035a internally mutes the sdo and sdo outputs when the device is not locked. when muted, sdo /sdo are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. the output data muting timing is shown in figure 14. fig. 14 output data muting timing 8. clock enable when clk_en is high, the gs9035a sco /sco outputs are enabled. when clk_en is low, the sco /sco outputs are set to a high z state and float to v cc . disabling the clock outputs results in a power savings of 10%. it is recommended that the clk_en input be hard wired to the desired state. for applications which do not require the clock output, connect clk_en to ground and connect the sco /sco outputs to v cc . 9. stressful data patterns all pll's are susceptible to stressful data patterns which can introduce bit errors in the data stream. pll's are most sensitive to patterns which have long run lengths of zeros or ones (low data transition densities for a long period of time). the gs9035a is designed to operate with low data transition densities such as the smpte 259m pathological signal (data transition density = 0.05). 10. pll design guidelines the performance of the gs9035a is primarily determined by the pll. thus, it is important that the system designer is familiar with the basic pll design equations. table 4: lock time relative to switching time switching time lock time <0.5s 10s 0.5s - 10ms 2t sys > 10ms 2t cycle + 2t sys lock ddi sdo valid data no data transitions valid data outputs muted
gennum corporation 522 - 41- 04 10 gs9035a a model of the gs9035a pll is shown below. the main components are the phase detector, the vco, and the external loop filter components. fig. 15 pll model 10.1. transfer function the transfer function of the pll is defined as o / i and can be approximated as equation 1 where n is the divider modulus d is the data density (=0.5 for nrz data) cp is the charge pump current in amps k is the vco gain in hz/v this response has 1 zero (w z ) and three poles (w p1 , w bw , w p2 ) where the bode plot for this transfer function is plotted in figure 16. fig. 16 bode plot for pll transfer function the 3db bandwidth of the transfer function is approximately 10.2. transfer function peaking there are two causes of peaking in the pll transfer function given by equation 1. the first is the quadratic which has and this response is critically damped for q = 0.5. thus, to avoid peaking: or therefore, w p2 > 4 w bw however, it is desirable to keep w p2 as low as possible to reduce the high frequency content on the loop filter. loop filter ? i ? o vco cp r lf k pd c lf1 c lf2 phase detector 2 k f + - n s o i ------ - sc lf1 r lf 1 + sc lf1 r lf l r lf ---------- ? ?? ?? 1 + --------------------------------------------------------------- - 1 s 2 c lf2 ls l r lf --------- 1 ++ --------------------------------------------------------- = l n di cp k ------------------- - = w z 1 c lf1 r lf ---------------------- - = w p1 1 c lf1 r lf l r lf --------- ? -------------------------------------- - = w bw r lf l --------- = w p2 1 c lf2 r lf ---------------------- - = w z 0 w p1 w bw w p2 frequency amplitude (db) w 3db w bw 12 w bw w p2 ----------- - ? w bw w p2 ? () 2 12 w bw w p2 ----------- - ? --------------------------------- - + ---------------------------------------------------------------------- w bw 0.78 ----------- - = s 2 c lf2 ls l r lf --------- 1 ++ w o 1 c lf2 l -------------------- = qr lf c lf2 l ------------ - = r lf c lf2 l ------------ - 1 2 -- - < 1 r lf c lf2 ---------------------- - l r lf --------- 4 >
gennum corporation 522 - 41- 04 11 gs9035a the second is the zero-pole combination: this causes lift in the transfer function given by to keep peaking to less than 0.05db, w z < 0.0057 w bw 10.3. selection of loop filter components based on the above analysis, select the loop filter components for a given pll bandwidth, 3db , as follows: 1. calculate where cp is the charge pump current and is a function of the r vco resistor and is obtained from figure 17. k = 90mhz/v for vco frequencies corresponding to the l curve. k = 140mhz/v for vco frequencies corresponding to the h curve. n is the divider modulus. ( l , h and n can be obtained from table 2 or table 3). 2. choose r lf = 2(3.14) 3db (0.78)l 3. choose c lf1 = 174 l / (r lf ) 2 4. choose c lf2 = l/4(r lf ) 2 fig. 17 charge pump current vs. r vco 10.4. spice simulations more detailed analysis of the gs9035a pll can be done using spice. a spice model of the pll is shown below: fig. 18 spice model of pll the model consists of a voltage controlled current source (g1), the loop filter components (r lf , c lf1 , and c lf2 ), a voltage controlled voltage source (e1), and a voltage source (v1). r2 is necessary to create a dc path to ground for node 1. v1 is used to generate the input phase waveform. g1 compares the input and output phase waveforms and generates the charge pump current, cp . the loop filter components integrate the charge pump current to establish the loop filter voltage. e1 creates the output phase waveform (phio) by multiplying the loop filter voltage by the value of the laplace transform (2pk /ns). the netlist for the model is given below. the .param statements are used to set values for cp , k , n, and d. cp is determined by the r vco resistor and is obtained from figure 17. sc lf1 r lf 1 + sc lf1 r lf l r lf ---------- - ? ?? ?? 1 + ---------------------------------------------------------- - s w z ------ - 1 + s w p1 --------- - 1 + ------------------- - = 20 log w p1 w z --------- - 20 log 1 1 w z w bw ----------- - ? --------------------- = l 2n i cp k --------------- = 0 50 100 150 200 250 300 350 400 0 200 400 600 800 1000 1200 1400 1600 1800 charge pump current (a) r vco ( ? ) phii phio r2 e1 r lf c lf1 c lf2 g1 v1 2 k ? in+ in- n s 1 lf note: phii, phio, lf and 1 are node names in the spice netlist.
gennum corporation 522 - 41- 04 12 gs9035a spice netlist * gs9035a pll model .param icp = 165e-6 kf= 90e+6 .param n = 1 d = 0.5 .param pi = 3.14 .ic v(phio) = 0 .ac dec 30 1k 10meg rlf 1 lf 1000 clf1 1 0 15n clf2 0 lf 15p e_laplace1 phio 0 laplace {v(lf)} {(2*pi*kf)/(n*s)} g1 0 lf value{d * icp/(2*pi)*v(phii, phio)} v1 2 0 dc 0v ac 1v r2 0 1 1g .end 11. i/o description 11.1. high speed inputs (ddi/ddi ) ddi/ddi are high impedance inputs which accept differential or single-ended input drive. two conditions must be observed when interfacing to these inputs: 1. input signal amplitudes are between 200 and 2000mv 2. the common mode input voltage range is as specified in the dc characteristics table. commonly used interface examples are shown in figures 19 and 20. figure 19 illustrates the simplest interface to the gs9035a. in this example, the driving device generates the pecl level signals (800mv amplitudes) having a common mode input range between 0.4 and 4.6v. this scheme is recommended when the trace lengths are less than 1in. the value of the resistors and the dc connection (v cc or ground), depends on the output driver circuitry of the previous device. fig. 19 simple interface to the gs9035a when trace lengths become greater than 1in, controlled impedance traces should be used. the recommended interface for differential signals is shown in figure 20. in this case, a parallel resistor (r load ) is placed near the gs9035a inputs to terminate the controlled impedance trace. the value of r load should be twice the value of the characteristic impedance of the trace. both traces should be in a symmetric arrangement and same physical transmission line dimensions since common-mode signals or common-mode noise is not terminated. in addition, series resistors, r source , can be placed near the driving chip to serve as source terminations. they should be equal to the value of the trace impedance. assuming 800mv output swings at the driver, r load =100 ? , r source =50 ? and z o = 50 ? . fig. 20 recommended interface for differential signals figure 21 shows the recommended interface when the gs9035a is driven single-endedly. in this case, the input must be ac-coupled and a matching resistor (z o ) must be used. fig. 21 recommended interface for single-ended driver 11.2. high speed outputs (sdo /sdo and sco /sco) sdo /sdo and sco /sco are current mode outputs that require external pullups ( see figure 22 ). note that no external pull-ups are required when used with the gs9020. the output signal swings are 800mv when 75 ? resistors are used. a diode can be placed between v cc and the pullups to shift the signal levels down by approximately 0.7 volts. when the output traces are longer than 1in, controlled impedance traces should be used. the pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75 ? ). fig. 22 high speed outputs with external pullups ddi ddi v cc or gnd v cc or gnd gs9035a ddi ddi r source r load r source z o z o gs9035a ddi ddi z o gs9035a v cc sdo sdo sco sco 75 ? 75 ? v cc 75 ? 75 ? gs9035a
gennum corporation 522 - 41- 04 13 gs9035a typical application circuit the figure below shows the gs9035a connected in a typical auto rate select smpte 259m application. table 4 summarizes the relevant system parameters. table 5: system parameters r vco = 365 ? , ? h = 540mhz, ? l = 360mhz smpte ss[2:0] data rate (mb/s) loop bandwidth 1 000 143 1.2mhz 1 001 177 1.9mhz 1 010 270 3.0mhz 1 011 360 4.5mhz 1 100 540 6.0mhz v cc v cc v cc v cc v cc v cc v cc v cc v cc 4 x 75 to gs9020 1 to led driver (optional) 10k 1800 15n 3.3p 4.7n 0.1 0.1 } from gs9024 r vco r lf c lf1 c lf2 ddi ddi v ee v ee v cc1 auto/man v ee smpte lock cosc v ee clk_en v ee v cc3 gs9035a top view lf+ lfs lf- r vco _rtn r vco cbg v cc2 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 sdo sdo sco sco sso ss1 ss2 all resistors in ohms, all capacitors in farads, unless otherwise shown. power supply decoupling capacitors are not shown. see application note "eb9035a" for details on pcb artwork. note 1. the 75 ? pullup resistors on sdo/sdo and sco/sco are not required when interfacing the gs9035a to the gs9020 since the gs9020 has internal 75 ? resistors. 365 (1%)
522 - 41- 04 14 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright july 1999 gennum corporation. all rights reserved. printed in canada. gs9035a package dimensions 12.319 min 11.582 max 11.430 min 12.573 max 1.270 x 45 1.219 1.067 seating plane min 0.508 4.572 max 4.115 min 3.048 max 2.286 min 11.582 max 11.430 min 12.319 min 12.573 max 10.922 max 9.906 min all dimensions in millimetres. 28 pin plcc (qm) revision notes: clarified symbols for pin numbers 22, 23, 24, and 25. for latest product information, visit www.gennum.com caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.

▲Up To Search▲

Price & Availability of GS9035ACPJ

	To Download GS9035ACPJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .